In Burst-mode high-speed data signal operations, serial signals are received on an infrequent basis and may have longer periods of inactivity than continuous mode applications. Although the burst-mode signals are known to be synchronous with a clock timing, they still require a clock and data recovery circuit to phase lock onto the signal. The conventional loop filter of a clock and data recovery circuit needs a long settling time if the phase relation to the incoming signal is not known. Minimizing the amount of settling time would be an advantageous improvement for Burst-mode high-speed serial transceivers.